Tutorials

T1: Introduction of CMOS Biosensor Design for Biomedical IoT Applications
by Kiichi Niitsu, Nagoya University, Japan.

T2: Portable and Scalable High Power Analog Mixed Signal Circuit Design for Automotive Applications in BiCMOS Processes
by Sri Navaneeth Easwaran, Texas Instruments Inc, USA.

T3: Neuromorphic Computing
by Arash Ahmadi, University of Windsor, Canada.

T4: Virtual prototyping of biosensor
by Morgan Madec, University of Strasbourg, France.

T5: Design of Efficient, Safe and Secure Embedded Systems with TTool
by Dominique Blouin, Telecom ParisTech, France.

T6: The Noise and the Jitter – The Domain Crossing Challenges
by Sri Raga Sudha Garimella, Solarflare Communications, USA.


Introduction of CMOS Biosensor Design for Biomedical IoT Applications
June 24, 2018, 8:30am – 12:00 noon

Kiichi Niitsu, Nagoya University, Japan

— Abstract — CMOS Biosensor is promising enabler for next-generation biomedical IoTs. This tutorial introduces CMOS biosensor design from fundamental to state-of-the-art. First, the tutorial introduces the fundamental of CMOS biosensors. Operational mechanismand applications of each types of CMOS biosensors such as potentiometric, amperometric, impedimetric, and ISFET are summarized. Latter part introduces development of energy-autonomous biomedical IoTs. Ensuring stable energy is one of the most important current challenges in wearable and implantable biomedical systems. For addressing this issue, many developments with respect to batteries, wireless power delivery, and energy harvesting have been reported. One of the promising candidates is bio fuel cell. In this tutorial, the fundamental and forecast of the bio-fuel-cell-operated biosensing systems. Firstly, I will summary the fundamental basics of bio fuel cell including operation mechanism, its performance, and its advantages/disadvantages. Secondary, I will introduce the examples of the bio-fuel-cell-operated biosensing systems. Thirdly, I will introduce the supply-sensing architecture presented in BioCAS 2015/2016 from our group. The supply-sensing architecture uses bio-fuel cells as both power source and sensing converter. In addition, I will plan to present the latest result on the work on Glucose-fuel-cell-operated Glucose sensing system which can be applied to self-powered continuous Glucose monitoring system (CGMS). The tutorial will conclude with a discussion of recent work and future applications on the bio-fuel-cell-operated biosensing systems.

— Bio — Kiichi Niitsu (S’05-M’10) was born in Japan, in 1983. He received the B.S. degree summa cum laude, M.S. and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 2006, 2008, and 2010, respectively. From 2010, he was an Assistant Professor at Gunma University,  Kiryu, Japan. Since 2012, he is currently a Lecturer at Nagoya University, Nagoya, Japan. Since 2015, he serves concurrently as Precursory Research for Embryonic Science and Technology (PRESTO) researcher, Japan Science and Technology Agency (JST). His current research interest lies in the low-power and high-speed technologies of analog and digital VLSI circuits for biomedical application.From 2008 to 2010, Dr. Niitsu was a Research Fellow of the Japan Society for the Promotion of Science (JSPS), a Research Assistant of the Global Center of Excellence (GCOE) Program at Keio University and a Collaboration Researcher of the Keio Advanced Research Center (KARC). He was awarded the 2006 KEIO KOUGAKUKAI Award, the 2007 INOSE Science Promotion Award, the 2008 IEEE SSCS Japan Chapter Young Researcher Award and the 2009 IEEE SSCS Japan Chapter Academic Research Award both from IEEE Solid-State Circuits Society Japan Chapter, the 2008 FUJIWARA Award from the FUJIWARA foundation, 2011 YASUJIRO NIWA Outstanding Paper Award, 2011 FUNAI Research Promotion Award, 2011 Ando Incentive Prize for the Study of Electronics, 2011 Ericsson Young Scientist Award, 2012 ASP-DAC University LSI Design Contest Design Award, NF Foundation R&D Encouragement Award, AKASAKI Award from Nagoya University, IEEE Nagoya Section Young Researcher Award, IEEE Biomedical Circuits and Systems Conference 2016 (BioCAS 2016) Best Paper Award, the 2017 Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology, the Young Scientists’ Prize, and the 2018 IEICE SUEMATSU-Yasuharu Award. He has published 51 referred original journal papers, 112 international conference papers, and 3 book chapters including 2 TBioCAS, 1 TCAS-I, 5 JSSC, 5 TVLSI, 2 ISSCC, 4 Symp. on VLSI Circuits, 9 BioCAS, 1 ISCAS, 1 CICC, 4 A-SSCC, 2 ICECS, 7 APCCAS. He served as a technical committee of IEEE biomedical circuits and systems (BioCAS TC), a Review Committee Member of ISCAS 2017/2018, a Technical Program Committee of ICECS 2018, a Review Committee Member of APCCAS 2014, an editorial committee of IEICE Transactions on Electronics, Special Section on Analog Circuits and Related SoC Integration Technologies, and an editorial committee of IEICE ESS Fundamental Review. He is a member of IEEE, IEICE (the Institute of Electronics, Information and Communication Engineers of Japan), and JSAP (the Japan Society of Applied Physics).


Portable and Scalable High Power Analog Mixed Signal Circuit Design for Automotive Applications in BiCMOS Processes
June 24, 2018, 8:30am – 12:00 noon

Sri Navaneeth Easwaran, Texas Instruments Inc, USA.

— Abstract — The electronic content is increasing in automotive applications replacing earlier mechanical and hydraulics solutions. However proper protection and diagnostic circuits are required to ensure that electronic components perform the expected function and achieve ultimate fail silent (fault tolerant) operation. These automotive circuits are not much different from the conventional analog circuits used in consumer electronics topology wise but have to handle a wide range of input voltage from 5V to 40V and wide range of currents from 30mA to 4A. There are several additional system requirements and design implementation challenges that have to be considered when defining and implementing automotive safety circuits. This tutorial introduces the State of the Art requirements of automotive ICs and discusses the power stages and their driver along with challenges due to R-L-C type of loads with the design solutions is presented. Such designs demand current sensing, limitation and protection. Different current sensing and limitation techniques are discussed. They need a good understanding of the junction temperature rise during the operation of these power stages and so an insight to thermal simulations will be presented. Test cases from high side driver, low side driver configurable high side/low side floating will be presented. These are used in several automotive applications for airbag, braking, power steering and solenoid drivers. After discussing about the power stages, the tutorial discusses about the fundamental issues that arise from the simple cross coupled level shifters in a multiple supply voltage design environment. The biasing circuitry for these power stages is discussed. The power supply sequencing and various fault scenarios will be presented. A robust solution using the current and voltage selector based circuits will be discussed. After the biasing circuits, the tutorial takes a deep look into the high voltage and negative voltage tolerant switches that are implemented for diagnostics in automotive applications. Finally the tutorial presents about the scalability and programmability of these designs. It does teach the minor design tricks and additional circuits that are needed while porting or redesigning the circuits from an older technology node like 0.35μM to 0.13μM. Structures for the proof of concept are simulated and measured. Tutorial does cover the strong and thermally activated parasitic bipolar transistor that gets activated unintentionally due to the negative voltage requirements. The aggressor and victim concepts will be presented from test cases. Such unintentional activation can cause catastrophic fails to the system and the tutorial presents the design and layout based mitigation methodology to avoid the interference of these parasitic in any technology node. As the electronic content is increasing in automotive, this tutorial will be valuable for the design community in general to carefully design high voltage fault tolerant circuits demanded by the automotive OEMs. However these circuits are not only limited to automotive but well applicable for industrial and consumer electronics.

— Bio — Sri Navaneeth Easwaran was born in Erode, India on October 19, 1977. After finishing his Higher Secondary school, he received his Bachelor of Engineering, B.E. Degree (cum laude) in Electronics and Communication Engineering from Shanmugha College of Engineering (affliated to Bharathidasan University, Tiruchirapalli, India), Thanjavur, India in 1998. He worked at SPIC Electronics, Chennai and STMicroelectronics, Noida, India between 1998 and 2000. From 2000 he worked for Philips Semiconductors at Bengaluru India, Zurich Switzerland and Nijmegen, The Netherlands where he designed analog circuits for Mobile Baseband and Power Management Units. While working at Philips Semiconductors, he also received the International M.Sc. degree in Electrical Engineering from the University of Twente, Enschede (Prof. Dr.ir. Bram Nauta’s ICD group), The Netherlands on the design of NMOS LDOs. From 2006 he started his work at Texas Instruments GmbH Freising, Germany and he joined the Technische Elektronik group at Friedrich-Alexander-Universität Erlangen-Nürnberg in January 2010 as an external Ph.D student under the supervision of Prof. Dr. –Ing. Dr. -Ing. habil. Robert Weigel. His research focused on the fault tolerant design of smart power drivers and diagnostic circuits. He received his Dr.-Ing degree from Friedrich-Alexander-Universität Erlangen-Nürnberg in May, 2017. Since September 2010 he is with Texas Instruments Inc, Dallas, Texas USA where he has the design lead for several airbag squib driver ICs. He has also designed analog high voltage, negative voltage tolerant circuits for automotive power steering and braking ICs. He was elected as the Senior Member of IEEE in 2011, Member Group Technical Staff at Texas Instruments in 2014. He has more than 15 patents (US and German) in the field of Analog Mixed Signal IC Design and has 6 IEEE and conference publications.


Neuromorphic Computing
June 24, 2018, 8:30am – 12:00 noon

Arash Ahmadi, University of Windsor, Canada.

— Abstract — The performance of von Neumann machine is greatly hindered by fundamental hardware and software design challenges such as power density, memory wall, performance, energy efficiency, security, privacy, reliability, sustainability, fault tolerance, scalability and flexibility. This is motivating the active research on new or alternative computing architectures. Neuromrphic computers, inspired by the central nervous system, offer a promising paradigm to build the next generation of massively parallel, energy efficient, real-time information processing systems. Efforts in hardware realization of practical neuro-processors are hampered by constrained design requirements, including non-linear numerical calculations, dense synaptic connectivity, large weight matrixes, event synchronizations, process variability and complex hierarchical structures. Emerging new design approaches and nano-devices are proven to be effective in emulating the massive parallelism and plasticity characteristics of the biological neural networks, including neurons, astrocytes, synaptic and non-synaptic plasticity, within a single device. In this tutorial we aim to investigate various approaches in designing and realizing neuromorphic hardware and their corresponding data coding and training functions for spiking neural networks, deep learning, and artificial intelligence applications. Understanding of the brain and its behavior has been an active research field targeting for variety of applications. Modeling and implementation of brain-like computing circuits and systems are considered important because of three main reasons: to provide more accurate tools and devices for medical and neuroscience studies, the possibility of creating prosthetic neural connections either for rehabilitation purposes or direct brain and machines interfaces, and exploring new computational paradigms to enrich or go beyond the standard computation models and architectures. Accordingly, neural systems, as the most powerful natural computers, have been the subject of research efforts ranging from mathematics to biology for decades. Among all the possibilities, utilizing well developed electronic components and circuits to mimic neurological behaviors, is considered as the main choice for direct implementation of the biologically plausible neuro-systems.

— Bio — Arash Ahmadi (IEEE S’04–M’08–SM’16) received the B.Sc. degree in electronics engineering from the Sharif University of Technology, Tehran, Iran, in 1993 and the M.Sc. degree from Tarbiat Modares University, Tehran, Iran, in 1997, and the Ph.D. degree in electronics from the University of Southampton, Southampton, U.K., in 2008. By completing his Ph.D., Dr. Ahmadi was granted a research fellowship grant in an EPSRC funded project, which was a collaboration between several universities and industrial partners including Cambridge, Southampton, Manchester and Sheffield universities as well as ARM, Silistix and Thales companies [15] {G11}. This project, focused on a massively parallel, fault tolerant and low power computing system consist of 10,000 networked ARM processors for neuromorphic and cognitive computing applications. After my postdoc fellowship, He joined Razi University as an Assistant Professor. During his work at Razi University, he initiated a research group in the field of hardware design and optimization working on variety of academic and industrial research projects focused on three major directions including: design and prototyping of neuromorphic, secure remote monitoring and control embedded systems for industrial applications, and hardware security and light-weight cryptography. Arash Ahmadi has experience of working on a variety of industrial funded projects and has founded a research group with more than 30 master and Ph.D. students. Since 2012, he has published more than 35 journal articles, 70 refereed conference papers and received considerable achievements and awards for my research and teaching excellence. He is currently an Associate Professor at the Electrical Engineering Department, Razi University, and a Visiting Scholar at the University of Windsor, Windsor, ON, Canada. His current research interests include neuromorphic, neural computing, artificial life, memristor, and embedded systems.


Virtual prototyping of biosensor
June 24, 2018, 1:30pm – 5:00pm

Morgan Madec, University of Strasbourg, France.

— Abstract — During the last decade, many applications at the interface between electronics and biotechnologies arise. Biosensors and Labs-on-chip are some examples among others. The efficient design of such systems requires to integrate biological part since the earlier steps for the design flow. Thus, adapted CAD tools are required. One way to achieve them is to extend existing design flow of electronics biochemistry. The tutorial addresses the following question “How could we efficiently couple models of electronic devices with those of the biochemical reactions?” The solution we suggest is a biohardware description language which is a text file that looks like a netlist. This description is translated directly into a SPICE equivalent model and can be then integrated in the model of complete electronics circuits.

— Bio — Morgan Madec is an associate professor the University of Strasbourg, France. He received the PhD degree in microelectronics from the University Louis Pasteur, Strasbourg, France in 2006. In 2008, he was recruited as associate professor and started working on the compact modeling of sensors (magnetic and optical). In 2011, he started a new research thematic on trying to extend CAD tools from microelectronics to ne new challenges met in biological engineering: synthetic biology, bio-sensors, lab-on-chips, etc..


Design of Efficient, Safe and Secure Embedded Systems with TTool
June 24, 2018, 1:30pm – 5:00pm

Dominique Blouin, Telecom ParisTech, France.

— Abstract — The design of modern embedded systems is more and more challenging since these systems are often realized as parallel systems in order to provide more computational power. These architectures are difficult to program because of their high degree of parallelism, the complex interactions between hardware and software components, their heterogeneous nature, and the diversity of properties they should satisfy (safety, security, performance). An important challenge is to efficiently design these systems in order to reduce their time-to-market and development costs. Among the possible approaches that can be taken to address this challenge, model-based engineering proposes to model the system at a higher level of abstraction in order to reduce complexity. Such models can be processed by EDA tools in order to detect design flaws early before implementation starts. In this hands-on tutorial, we will introduce SysML-Sec, a modeling environment for the design of efficient, safe and secure embedded systems that is supported by TTool, a free and open-source toolkit. The main strengths of TTool is its ease of use and automated facilities: intensive simulation, formal verification and automated code generation can be performed with a press-button approach from SysML diagrams.

— Bio — Dominique Blouin obtained an M. Sc. in physics (astrophysics) from the University of British Columbia (Canada) in 1994 and a PhD in computer science from the University of South-Brittany (France) in 2013. He was a software architect at Cassiopae (France) until 2008 when he joined the Lab-STICC at the University of South-Brittany as a research engineer. After a post doc in the system analysis and modeling group of the Hasso Plattner institute in Potsdam (Germany) in 2015, he joined LabSoc in 2016 as a research engineer at Telecom ParisTech in the Communication and Electronics department. He is a contributor of TTool and his research interests are model-based and requirements engineering, computer-aided design tools, model transformation and synchronization and domain-specific languages for embedded systems.


The Noise and the Jitter – The Domain Crossing Challenges
June 24, 2018, 1:30pm – 5:00pm

Sri Raga Sudha Garimella, Solarflare Communications, USA.

— Abstract — Noise and jitter are the major constraints in modern high-speed processing and communication systems. With increasing noise, it is critical to recover the signal, process and transmit or receive the signal. Jitter imposes limitations to the maximum signaling rate for which the bit error rate (BER) does not exceed its maximum acceptable level, the minimum spacing between channels in order to avoid inter channel interference, etc. In the systems where both Digital and Analog blocks exist, the noise and jitter can propagate from analog domain to digital domain and vice versa. It would be very desirable to know the noise and jitter impacts in any IC design especially when the chip contains both the analog and digital blocks. This tutorial offers basic and high-level descriptions and challenges to Noise and Jitter focusing on the domain crossing challenges. The relation between noise and jitter is studied in detail, The Noise and Jitter are studies in Analog domain with adequate analysis on the circuits including PLLs. The noise and jitter propagation from the analog to digital blocks and vice versa are described. The propagation, analysis and challenges of off chip, on board noise and jitter circuits and the challenges of Transmitter, receiver design are described up to enough depth.

— Bio — Sri Garimella received her Bachelor’s degree with honors from the Computer Science Department from JNT University, India in 2003 and her Master’s degree in Electrical and Computer Engineering from New Mexico State University, NM in 2007 with highest student honor award “Outstanding Graduating Graduate Student Award”. She is also doing PhD in the same University from 2016 with research in Analog IC Design. She worked for Intel as a DDR Interface Design Engineer from 2008-16 and designed /validated high-speed Analog circuits whilst handling power performance trade-offs and Signal Integrity challenges. She is currently working at Solarflare Communications as Staff Analog Design Engineer. She has been a continuous researcher on improving the Analog circuit performance at higher speeds and worked on PLLs, ADC, Transmitter, Receiver, Signal Integrity etc. She presented a tutorial on “Signal Integrity in DDR Interface technologies” at MWSCAS 2017, and is the coauthor for 18 student/research papers published in various IEEE conferences and journals. She acted as paper reviewer for more than 11 conferences during her study and work at Industry.